K-Map Generator

This Karnaugh Map solver generates and minimizes K-Maps for 2 to 6 variables, producing simplified SOP and POS expressions with automatic grouping. Enter a boolean expression, minterms, or maxterms to visualize prime implicant groups, view the minimized output in Verilog or VHDL, and generate a gate-level circuit diagram.

• Supports 2–6 variables. Enter them comma-separated (e.g. A, B, C, D).
• Operators are flexible — you can mix symbols and words freely: A * B + C' and A and B or not C are both valid, even A * B or !C.
• Multiple symbols per gate: NOT is ' ~ !, AND is . * &, OR is + |, XOR is ^, XNOR is @, NAND is %, NOR is #.
• Precedence: NOT → AND/NAND → XOR/XNOR → OR/NOR. Use parentheses to override.
• Leave the expression blank and click Generate to enter manual mode — click cells directly to set 1, 0, or X.
• Switch to Minterms/Maxterms mode to enter indices directly (e.g. 1, 3, 5, 7).
• Click any cell in the K-map to toggle between 0, 1, and X (don't-care) — works in all modes. Click Revert to input or re-click Generate to restore the original values.
• Toggle POS, Verilog, VHDL, and Steps with the buttons below Generate.
• XOR/XNOR patterns are auto-detected when the SOP can be simplified using XOR gates.