Building Blocks
The fundamental components and conventions used throughout these topics. Start here if terms like "full adder", "gate delay", or "FA-eq" are unfamiliar.
- Logic Gates
AND, OR, XOR, NOT: the atomic units of digital hardware.
- Full Adder (FA)
Adds three 1-bit inputs (A, B, carry-in) producing a sum and carry-out.
- Measurement Conventions
What FA-eq, gate delays, and other notation in these topics mean.
- Two's Complement
The standard way hardware represents negative integers.
- Partial Products
The intermediate terms generated during binary multiplication.
- Carry Save Adder (CSA)
Adds three numbers producing two (sum + carry) with zero propagation delay.
- Circuit Diagrams
From boolean expressions to gate-level circuits.
- Sign Extension
Widening a signed number from N to M bits without changing its value.
- Overflow Detection
How hardware knows when an arithmetic result doesn’t fit.
- Fixed-Point Representation
Representing fractional numbers without a floating-point unit.
- Priority Encoder
Given multiple active inputs, finding the highest-priority one quickly.
- Barrel Shifter
Shifting by a variable amount in O(log n) delays.
- Comparator Circuits
How hardware compares two binary numbers to determine greater, less, or equal.
- FIFO Queues in Hardware
First-in-first-out buffers: the fundamental building block for pipelining, buffering, and order matching.
- Karnaugh Maps
A visual method for simplifying Boolean expressions by grouping adjacent cells.
- Flip-Flops & Latches
How hardware remembers: level-sensitive latches vs edge-triggered flip-flops.
- Finite State Machines
How hardware makes decisions that depend on history: states, transitions, and outputs.
Timing & Performance
Hardware speed is limited by how fast signals propagate through gates and wires. Understanding critical paths, setup/hold constraints, and the area-speed tradeoff is essential for designing circuits that meet timing at a target clock frequency.
- Critical Path
The slowest signal path that limits clock speed.
- Gate Delay & Propagation
Why outputs don’t change instantly when inputs change.
- Setup & Hold Time
When data must be stable relative to the clock edge.
- Pipelining
Increasing throughput by breaking a slow path into register stages.
- Area vs Speed Tradeoffs
Why making a circuit faster usually costs more hardware.
- Pipeline Hazards
Data, control, and structural hazards: what breaks pipelining and how hardware fixes it.
Multiplier Architectures
Binary multiplication in hardware has three stages: partial product generation (AND gates), partial product reduction (the core architectural choice), and final addition (carry-propagate adder). Architectures differ in how they organize reduction: sequentially reusing one adder, or in parallel across a 2D array or tree. The fundamental tradeoff: more combinational hardware buys less delay.
- Shift-and-Add
Sequential multiplication using one adder, reused n times.
- Booth's Algorithm (Radix-2)
Recodes the multiplier to skip runs of 1s and handle signed natively.
- Array Multiplier
Parallel n×n grid of adders with regular, layout-friendly structure.
- Wallace Tree
Logarithmic reduction tree: fastest with a CLA final adder.
Final-stage Adders
The final stage of any parallel multiplier is a carry-propagate addition of two rows. The choice of adder directly impacts total delay. These architectures also stand alone as general-purpose binary adders.
- Ripple Carry Adder (RCA)
Simplest adder: carry ripples bit-by-bit from LSB to MSB.
- Carry Lookahead Adder (CLA)
Computes all carries in parallel using generate/propagate logic.
- Carry Select Adder (CSeA)
Speculates on carry-in, computes both options, selects with a MUX.
Number Systems
How hardware encodes different kinds of numbers: signed integers, fractions, and real numbers with wide dynamic range. The representation determines what arithmetic the hardware can do and how much it costs.
- IEEE 754 Floating Point
How hardware represents real numbers with wide dynamic range.
- Endianness
Big-endian vs little-endian: how multi-byte values map to memory addresses.
Order Book & Matching
How electronic exchanges organize buy and sell orders, match them, and execute trades. These data structures and algorithms are implemented in FPGA-based matching engines at trading firms, where nanosecond-level latency matters: making this a direct application of hardware engineering.
- Order Book Mechanics
How limit order books organize bids, asks, and the spread: the core data structure of every electronic exchange.
- Matching Engines & Hardware
How orders are matched, why FPGA implementations dominate, and why this matters for hardware engineers.
- Market Data Infrastructure
How market data travels from exchanges to trading firms: UDP feeds, co-location, and FPGA network cards.
Memory Hierarchy
Processors are fast; main memory is slow. Caches bridge this gap by keeping recently and nearby data close to the CPU. Understanding how addresses map to cache locations, why some access patterns thrash, and how associativity and block size affect hit rate is fundamental to writing fast software and designing efficient hardware.
- Cache Memory
How CPU caches map addresses to fast local storage using tag, index, and offset bits.
- Write Policies
Write-through vs write-back: when and how cached writes reach main memory.
- Cache Replacement Policies
LRU, FIFO, and Random: how caches decide which line to evict.