Multiplier architecture visualizer

Four multiplier architectures run on the same operands and race against each other, each finishing in proportion to its real gate delay. Watch partial products get generated and reduced step by step, and compare how each design trades area for speed.

• Enter operands A and B in decimal, binary (0b1010), octal (0o200) or hex (0xFF).
• Pick a bit width (4, 8, 12 or 16) and tick the architectures to compare.
• Click Compute product, then use the playback controls to animate the reduction. Step advances one gate delay at a time; the line under each diagram explains the current step.
• The comparison table lists area in full-adder equivalents, delay in gate delays, and their product.
• Booth radix-2 recodes the multiplier into {−1, 0, +1} digits, so a run of ones costs one subtract and one add. Partial products shown in red are subtracted. It handles signed operands directly.
• Signed mode: shift-and-add subtracts the last row, because B's top bit weighs −2ⁿ⁻¹. Array and Wallace use the modified Baugh-Wooley scheme: bits that involve exactly one sign bit are inverted (shown with a bar over them), and a row of 1s at columns n and 2n−1 corrects the sum.
• Wallace tree finishes with a carry-propagate adder of your choice (ripple carry or carry lookahead).
• Choose Signed (two's complement) to read the operands and the 2n-bit result as signed integers.