Multiplier Visualizer

This binary multiplier visualizer lets you compare Shift-and-Add, Booth's Radix-2, Array, and Wallace Tree multiplier architectures side by side. Animate partial product generation and reduction step by step to understand how each design trades off area for speed, and see signed multiplication with Booth encoding in action.

• Enter two operands (A and B) in decimal, bin (0b1010), octal (0o200) or hex (0xFF).
• Select bit width (4, 8, 12, or 16) and check which architectures to compare.
• Click Compute to see the result, then use playback controls to animate partial product reduction.
• The race view shows all selected architectures simultaneously — each finishes proportional to its actual gate delay.
• Step (▶|) advances one gate delay at a time. The description below each diagram explains the current step.
• The summary table compares area (full-adder equivalents), delay (gate delays), and area×delay product.
• Booth's (Radix-2) encodes the multiplier into {−1, 0, +1} digits, skipping runs of 1s. Partial products shown in red are subtracted. Handles signed multiplication natively.
• Wallace Tree uses a selectable final carry-propagation adder (RCA or CLA).
• Toggle Signed (2's complement) to interpret operands and the 2n-bit result as signed integers.