Cache simulator
Configure a small CPU cache and step through memory accesses to see how addresses map to sets, when lines hit or miss, and which line gets evicted.
How it works
Access memory addresses and watch how a CPU cache maps, stores and evicts data. Step through preset access patterns to see spatial locality, temporal locality, thrashing and conflict misses across direct-mapped, set-associative and fully associative configurations with LRU, FIFO and random replacement.
Configure the cache with the selectors in the panel below. Block size sets how many consecutive bytes are fetched together (spatial locality). Cache lines sets the total capacity. Associativity sets how many ways each set has: more ways means fewer conflict misses but more hardware. The replacement policy (LRU, FIFO or random) decides which line is evicted when a set is full.
Access addresses by typing a number from 0 to 255 and choosing Access address, or load a pattern and step through it with Next access or the space bar.
Watch the breakdown under the address field. It shows how each address splits into tag, index and offset bits, which decides where the data maps in the cache.
Try different configurations with the same pattern. Load Thrashing in direct-mapped mode, then switch to 2-way and reload to see associativity remove the conflict misses.
Bit split formulas
| Field | Formula | Example (default) |
|---|---|---|
| Offset bits | log2(block size) | log2(4) = 2 |
| Index bits | log2(cache lines / associativity) | log2(8 / 1) = 3 |
| Tag bits | address bits − index bits − offset bits | 8 − 3 − 2 = 3 |
| Number of sets | cache lines / associativity | 8 / 1 = 8 |