Latency Simulator

This simulator shows how a trading order travels through a processing pipeline — from network arrival to fill confirmation. Each stage has a latency in nanoseconds, and the total tick-to-trade time is the sum of all stages.

Latency ranges: Real-world software tick-to-trade is typically 5–50 µs for competitive firms. FPGA-accelerated paths achieve 0.5–2 µs. FPGA latencies aren't truly constant — they're deterministic with very low jitter (nanosecond variance), compared to software which has microsecond-level jitter from context switches, cache misses, and garbage collection. The default values here model a competitive software firm vs an FPGA setup. Edit the latencies to explore “what if” scenarios.

The pipeline shows each processing stage as a box. When an order flows through, stages light up in sequence. The latency breakdown bar below shows the proportional time spent at each stage.

Send Order pushes a new order into the pipeline. In auto mode it animates through all stages. In step mode, press "Next Step" or spacebar to advance one stage at a time.

Compare Mode shows two pipeline paths side by side (e.g., software vs FPGA). Send an order and watch both paths process simultaneously to see where the FPGA saves time.

Edit latencies by changing the nanosecond values in the Controls panel. This lets you model "what if risk check was slower?" or "what if we moved to colocation?"

Scenarios preset the pipeline configuration and queue orders to demonstrate specific concepts: baseline paths, FPGA acceleration, colocation effects, burst traffic queuing, and pipeline bottlenecks.

Burst mode sends multiple orders to show queuing effects. When the pipeline is busy, incoming orders wait — their total latency includes queue time plus processing time.