Array Multiplier
Parallel n×n grid of adders with regular, layout-friendly structure.
Problem
How do you multiply in parallel without complex tree routing?
How it works
A regular n×n grid of AND gates generates all partial products simultaneously. Full adders arranged in rows reduce partial products: carries propagate diagonally through the array, then ripple across the bottom row.
Key insightThe perfectly regular 2D structure maps directly to silicon layout: easy to design, route, and manufacture.
Tradeoffs
- Area
- n² FA-eq
- Delay
- 4(n−1) gate delays
- Best when: Layout regularity matters more than absolute speed.