Measurement Conventions
What FA-eq, gate delays, and other notation in these topics mean.
Problem
How do we compare hardware architectures fairly? We need standard units for area (size) and delay (speed).
How it works
Gate delay: the time for one logic gate (AND, OR, etc.) to switch its output. This is the fundamental unit of speed. A circuit with "10 gate delays" means a signal must pass through 10 gates in sequence on the critical path. Real gate delays are ~10–100 picoseconds depending on technology, but the count lets us compare architectures independent of manufacturing process.
FA-eq (full adder equivalent): a normalized unit of area. One FA-eq equals the silicon area of one full adder (~5 gates). Not every component is a full adder, but we can express any circuit's area in terms of "how many FAs worth of silicon." For example, a CLA's lookahead logic is AND/OR gates, not FAs, but we convert its gate count to FA-eq for comparison.
n: the bit width of the operands (e.g., n=8 means 8-bit inputs).
MSB / LSB: Most / Least Significant Bit. MSB is the leftmost (highest-value) bit; LSB is the rightmost (bit 0).
CPA: Carry-Propagate Adder. A generic term for any adder that produces a final sum (RCA, CLA, etc.). Used in Wallace Tree context: the tree reduces to 2 rows, then a CPA finishes.
MUX (multiplexer): a selector switch. Given multiple inputs and a select signal, it outputs the chosen input. Used in Carry Select adders to pick between the carry=0 and carry=1 result.
FA-eq (full adder equivalent): a normalized unit of area. One FA-eq equals the silicon area of one full adder (~5 gates). Not every component is a full adder, but we can express any circuit's area in terms of "how many FAs worth of silicon." For example, a CLA's lookahead logic is AND/OR gates, not FAs, but we convert its gate count to FA-eq for comparison.
n: the bit width of the operands (e.g., n=8 means 8-bit inputs).
MSB / LSB: Most / Least Significant Bit. MSB is the leftmost (highest-value) bit; LSB is the rightmost (bit 0).
CPA: Carry-Propagate Adder. A generic term for any adder that produces a final sum (RCA, CLA, etc.). Used in Wallace Tree context: the tree reduces to 2 rows, then a CPA finishes.
MUX (multiplexer): a selector switch. Given multiple inputs and a select signal, it outputs the chosen input. Used in Carry Select adders to pick between the carry=0 and carry=1 result.
Key insightFA-eq measures how much silicon you need (area/cost). Gate delays measure how fast the critical path is (speed). The core tradeoff in hardware design: spending more area (FA-eq) to reduce delay (gate delays).