Matching Engines & Hardware
How orders are matched, why FPGA implementations dominate, and why this matters for hardware engineers.
Problem
Once orders are in the book, how does the exchange decide which orders trade against each other? And why do trading firms implement this in hardware?
How it works
Matching (crossing) occurs when a new order's price crosses the spread:
• New buy at price P where P ≥ best ask → match against resting asks, starting at best ask, FIFO within each level.
• New sell at price P where P ≤ best bid → match against resting bids, starting at best bid, FIFO within each level.
Partial fills: if a buy for 100 hits a resting ask of 60, the ask is fully filled (removed), 40 remaining continues matching at the next level. If no more levels cross, the remainder rests in the book as a new bid.
The aggressor is the incoming order that initiates the match. Trade records track which side was the aggressor: this is how exchanges classify trades as "buy-initiated" or "sell-initiated."
Why hardware? Exchange matching engines at firms like Nasdaq, CME, and proprietary trading firms are implemented on FPGAs for sub-microsecond latency: published figures from firms like Optiver and Xilinx research cite latencies in the hundreds of nanoseconds. The matching algorithm is simple: sorted insert + FIFO queue operations: but the requirement is deterministic latency: every order processed in the same number of clock cycles regardless of book state. Software engines can't guarantee this due to OS scheduling, cache misses, and memory allocation overhead. Even optimized C++ engines typically land in the single-digit microsecond range: an order of magnitude slower. FPGA implementations pipeline the comparison, insertion, and matching stages, achieving wire-speed processing with fixed, predictable timing on every order.
• New buy at price P where P ≥ best ask → match against resting asks, starting at best ask, FIFO within each level.
• New sell at price P where P ≤ best bid → match against resting bids, starting at best bid, FIFO within each level.
Partial fills: if a buy for 100 hits a resting ask of 60, the ask is fully filled (removed), 40 remaining continues matching at the next level. If no more levels cross, the remainder rests in the book as a new bid.
The aggressor is the incoming order that initiates the match. Trade records track which side was the aggressor: this is how exchanges classify trades as "buy-initiated" or "sell-initiated."
Why hardware? Exchange matching engines at firms like Nasdaq, CME, and proprietary trading firms are implemented on FPGAs for sub-microsecond latency: published figures from firms like Optiver and Xilinx research cite latencies in the hundreds of nanoseconds. The matching algorithm is simple: sorted insert + FIFO queue operations: but the requirement is deterministic latency: every order processed in the same number of clock cycles regardless of book state. Software engines can't guarantee this due to OS scheduling, cache misses, and memory allocation overhead. Even optimized C++ engines typically land in the single-digit microsecond range: an order of magnitude slower. FPGA implementations pipeline the comparison, insertion, and matching stages, achieving wire-speed processing with fixed, predictable timing on every order.
Key insightThe matching engine is one of the most direct real-world applications of the data structures and hardware design principles covered elsewhere on this site: priority queues map to comparator trees, FIFO order queues map to RAM-based circular buffers with read/write pointers, and the entire pipeline maps to the same area-vs-speed tradeoffs seen in adder and multiplier architectures.