p14m

Comparator Circuits

How hardware compares two binary numbers to determine greater, less, or equal.

Problem

How does hardware answer "is A > B?" in a single clock cycle? This is the core operation behind priority queues, sorting networks, and matching engines.

How it works

1-bit comparator: compares two bits A and B, producing three outputs: A>B, A=B, A<B.
• A>B = A · ¬B
• A<B = ¬A · B
• A=B = A ⊙ B (XNOR)

N-bit magnitude comparator: compares from the MSB down. At each bit position, if the bits differ, the comparison is decided: the number with a 1 in that position is greater. If the bits are equal, move to the next position. If all bits are equal, the numbers are equal.

Cascaded comparators: for wide operands, smaller comparators (e.g., 4-bit) can be cascaded. The high comparator’s result takes priority; the low comparator’s result is only used when the upper bits are equal. This is like carry propagation in adders: and the same acceleration techniques (lookahead, tree structures) apply.

In practice: subtraction-based comparison (compute A−B and check the sign/borrow) is often used since the ALU already has a subtractor. But dedicated comparator trees are faster when you only need the comparison result, not the difference.
Key insightComparison is a cascaded decision from MSB to LSB: the first bit position where A and B differ determines the result. A ripple comparator has O(n) delay for n-bit numbers; tree-structured comparators reduce this to O(log n), the same speedup that CLA gives over RCA. Trading firms use these tree comparators in FPGA matching engines to check "does this order’s price cross the spread?" in minimal clock cycles.