Critical Path
The slowest signal path that limits clock speed.
Problem
What determines the maximum clock frequency of a digital circuit?
How it works
The critical path is the longest combinational delay between any register output and any register input (or between primary inputs and outputs in purely combinational circuits). The clock period must be at least as long as this worst-case delay, or the circuit produces incorrect results.
To find the critical path: trace every possible signal path through the combinational logic, sum the gate delays along each path, and identify the maximum. That path is the bottleneck.
Example: RCA vs CLA: In a 16-bit RCA, the critical path is the carry chain from bit 0 to bit 15: 32 gate delays. In a 16-bit CLA, the lookahead logic computes all carries in parallel, so the critical path is only ~8 gate delays. Same function, vastly different critical paths.
Reducing the critical path is the central goal of most hardware optimization. Techniques include pipelining (insert registers to break long paths), parallelism (CLA instead of RCA), and speculation (Carry Select).
To find the critical path: trace every possible signal path through the combinational logic, sum the gate delays along each path, and identify the maximum. That path is the bottleneck.
Example: RCA vs CLA: In a 16-bit RCA, the critical path is the carry chain from bit 0 to bit 15: 32 gate delays. In a 16-bit CLA, the lookahead logic computes all carries in parallel, so the critical path is only ~8 gate delays. Same function, vastly different critical paths.
Reducing the critical path is the central goal of most hardware optimization. Techniques include pipelining (insert registers to break long paths), parallelism (CLA instead of RCA), and speculation (Carry Select).
Key insightThe critical path is the single bottleneck that limits your clock speed. Every optimization technique in digital design is ultimately about shortening it.