Pipelining
Increasing throughput by breaking a slow path into register stages.
Problem
A combinational circuit has a long critical path limiting your clock speed. How do you increase throughput without redesigning the logic?
How it works
Insert registers at intermediate points in the combinational logic to split one long path into K shorter stages. Each stage completes in 1/(K) of the original delay, so the clock can run K× faster.
Throughput vs latency: pipelining increases throughput (results per second) but not latency (time for one result). A 4-stage pipeline produces one result per cycle at a 4× faster clock, but each individual result still takes 4 cycles to complete.
Example: multiplier: A combinational array multiplier for 16-bit operands might have a critical path of 60 gate delays. Splitting it into 4 pipeline stages (15 gate delays each) allows the clock to run 4× faster. Once the pipeline is full, you get one 16-bit product every cycle.
Cost: each pipeline stage adds a register (N flip-flops wide), increasing area and power. There’s also a diminishing return: register overhead (setup time + clock-to-Q delay) eats into the speedup as stages get very short.
Throughput vs latency: pipelining increases throughput (results per second) but not latency (time for one result). A 4-stage pipeline produces one result per cycle at a 4× faster clock, but each individual result still takes 4 cycles to complete.
Example: multiplier: A combinational array multiplier for 16-bit operands might have a critical path of 60 gate delays. Splitting it into 4 pipeline stages (15 gate delays each) allows the clock to run 4× faster. Once the pipeline is full, you get one 16-bit product every cycle.
Cost: each pipeline stage adds a register (N flip-flops wide), increasing area and power. There’s also a diminishing return: register overhead (setup time + clock-to-Q delay) eats into the speedup as stages get very short.
Key insightPipelining doesn’t make any single computation faster: it lets you overlap multiple computations so the throughput increases by the number of stages.