Pipeline Hazards
Data, control, and structural hazards: what breaks pipelining and how hardware fixes it.
Problem
Pipelining overlaps instruction execution for higher throughput. But what happens when instruction 2 needs the result of instruction 1, which hasn't finished yet?
How it works
Data hazards (RAW): Read After Write. Instruction B reads a register that instruction A hasn't written back yet. Example:
Without forwarding: the pipeline must stall (insert bubble cycles) until the result is available. A 2-cycle stall per dependency devastates throughput.
Forwarding (bypassing): the result is available at the EX stage output before it's written to the register file. Hardware adds multiplexers that route the EX or MEM stage result directly to the next instruction's ALU input. This eliminates most stalls.
Load-use hazard: one case forwarding can't fully solve. A load instruction's data isn't available until the end of the MEM stage. If the very next instruction needs that value for EX, a 1-cycle stall is unavoidable. Compilers reorder instructions to fill this slot when possible (delay slot scheduling).
Control hazards: branch instructions change the PC, but the pipeline has already fetched the next sequential instructions. Options: stall until the branch resolves (expensive), predict the branch direction (modern CPUs: ~95% accuracy), or flush the pipeline on misprediction.
Structural hazards: two instructions need the same hardware resource in the same cycle (e.g., one memory port for both instruction fetch and data load). Solved by duplicating resources (separate instruction and data caches).
ADD R1, R2, R3: writes R1 in WB stage (cycle 5)SUB R4, R1, R5: needs R1 in ID stage (cycle 3)Without forwarding: the pipeline must stall (insert bubble cycles) until the result is available. A 2-cycle stall per dependency devastates throughput.
Forwarding (bypassing): the result is available at the EX stage output before it's written to the register file. Hardware adds multiplexers that route the EX or MEM stage result directly to the next instruction's ALU input. This eliminates most stalls.
Load-use hazard: one case forwarding can't fully solve. A load instruction's data isn't available until the end of the MEM stage. If the very next instruction needs that value for EX, a 1-cycle stall is unavoidable. Compilers reorder instructions to fill this slot when possible (delay slot scheduling).
Control hazards: branch instructions change the PC, but the pipeline has already fetched the next sequential instructions. Options: stall until the branch resolves (expensive), predict the branch direction (modern CPUs: ~95% accuracy), or flush the pipeline on misprediction.
Structural hazards: two instructions need the same hardware resource in the same cycle (e.g., one memory port for both instruction fetch and data load). Solved by duplicating resources (separate instruction and data caches).
Key insightForwarding is the key optimization. It works because the result exists inside the pipeline before it's written back: you just need wires (and muxes) to route it where it's needed. The only stall that remains in a well-designed pipeline is the 1-cycle load-use penalty.