Setup & Hold Time
When data must be stable relative to the clock edge.
Problem
A flip-flop captures data on the clock edge. How long must the data be stable before and after that edge?
How it works
Setup time (tsu): the minimum time data must be stable before the active clock edge. If data changes too close to the edge, the flip-flop may capture the wrong value or enter metastability.
Hold time (thold): the minimum time data must remain stable after the active clock edge. Changing data too soon after the edge can corrupt the captured value.
The timing window: data must be stable during the interval [tclk − tsu, tclk + thold]. Outside this window, data is free to change.
Setup violation means the combinational logic between two flip-flops is too slow: the fix is a faster critical path or a slower clock. Hold violation means the logic is too fast: signals race through before the capturing flip-flop is done. The fix is adding delay (buffer insertion).
Metastability: if setup or hold is violated, the flip-flop output may hover at an intermediate voltage for an unpredictable time before eventually settling to 0 or 1. This is especially dangerous at clock domain crossings.
Hold time (thold): the minimum time data must remain stable after the active clock edge. Changing data too soon after the edge can corrupt the captured value.
The timing window: data must be stable during the interval [tclk − tsu, tclk + thold]. Outside this window, data is free to change.
Setup violation means the combinational logic between two flip-flops is too slow: the fix is a faster critical path or a slower clock. Hold violation means the logic is too fast: signals race through before the capturing flip-flop is done. The fix is adding delay (buffer insertion).
Metastability: if setup or hold is violated, the flip-flop output may hover at an intermediate voltage for an unpredictable time before eventually settling to 0 or 1. This is especially dangerous at clock domain crossings.
Key insightSetup time constrains how fast your clock can run. Hold time constrains how fast your logic can be. Both must be satisfied simultaneously for correct operation.