Gate Delay & Propagation
Why outputs don’t change instantly when inputs change.
Problem
When an input changes, why doesn’t the output change immediately?
How it works
Every logic gate has a finite propagation delay (tpd): the time from when an input changes to when the output settles to its new value. This delay exists because transistors need time to charge and discharge internal capacitances.
Typical values in modern CMOS: an inverter is ~10–20 ps, a 2-input NAND is ~15–30 ps. Larger fan-in gates (e.g., 4-input AND) are slower because more transistors are stacked in series.
Rise vs fall time: tpLH (low-to-high) and tpHL (high-to-low) are often different because PMOS and NMOS transistors have different drive strengths. Datasheets usually report the worst case.
Contamination delay (tcd) is the minimum delay: the earliest the output might start changing. This matters for hold-time analysis. The window between tcd and tpd is when the output is potentially unstable.
In our abstract models, we count "gate delays" as uniform units. In real design, each gate type has a different delay, and synthesis tools optimize by choosing gate sizes and topologies.
Typical values in modern CMOS: an inverter is ~10–20 ps, a 2-input NAND is ~15–30 ps. Larger fan-in gates (e.g., 4-input AND) are slower because more transistors are stacked in series.
Rise vs fall time: tpLH (low-to-high) and tpHL (high-to-low) are often different because PMOS and NMOS transistors have different drive strengths. Datasheets usually report the worst case.
Contamination delay (tcd) is the minimum delay: the earliest the output might start changing. This matters for hold-time analysis. The window between tcd and tpd is when the output is potentially unstable.
In our abstract models, we count "gate delays" as uniform units. In real design, each gate type has a different delay, and synthesis tools optimize by choosing gate sizes and topologies.
Key insightGate delay is the atomic unit of hardware speed. Every timing analysis: critical path, setup/hold, pipelining: starts with knowing how long each gate takes.