Flip-Flops & Latches
How hardware remembers: level-sensitive latches vs edge-triggered flip-flops.
Problem
Logic gates are combinational: their output depends only on current inputs, with no memory. How does hardware store a bit?
How it works
SR latch: two cross-coupled NOR (or NAND) gates form a feedback loop. Setting S=1 stores a 1; setting R=1 stores a 0. The output holds its value when both inputs are 0. Problem: S=R=1 is undefined (forbidden state).
D latch: adds a gate to ensure only one of S/R is active. When Enable is high, the output follows the D input (transparent). When Enable goes low, the output latches and holds the last value of D. Problem: while the latch is transparent, any glitch on D passes straight through.
D flip-flop (edge-triggered): two D latches in series with inverted enable signals (leader-follower). The output changes only on the rising edge of the clock. During the rest of the cycle, the output is stable regardless of what D does. This is what makes synchronous design work: all flip-flops sample simultaneously at the clock edge, giving combinational logic a full cycle to settle.
Other types:
• T flip-flop: toggles its output when T=1. Used in counters.
• JK flip-flop: like SR but J=K=1 toggles instead of being undefined. General-purpose but D is simpler and dominates modern design.
Setup and hold: D must be stable for a window around the clock edge: setup time before, hold time after. Violating these causes metastability: the flip-flop output can float at an intermediate voltage, potentially for an unpredictable duration.
D latch: adds a gate to ensure only one of S/R is active. When Enable is high, the output follows the D input (transparent). When Enable goes low, the output latches and holds the last value of D. Problem: while the latch is transparent, any glitch on D passes straight through.
D flip-flop (edge-triggered): two D latches in series with inverted enable signals (leader-follower). The output changes only on the rising edge of the clock. During the rest of the cycle, the output is stable regardless of what D does. This is what makes synchronous design work: all flip-flops sample simultaneously at the clock edge, giving combinational logic a full cycle to settle.
Other types:
• T flip-flop: toggles its output when T=1. Used in counters.
• JK flip-flop: like SR but J=K=1 toggles instead of being undefined. General-purpose but D is simpler and dominates modern design.
Setup and hold: D must be stable for a window around the clock edge: setup time before, hold time after. Violating these causes metastability: the flip-flop output can float at an intermediate voltage, potentially for an unpredictable duration.
Key insightThe D flip-flop is the universal storage element in synchronous digital design. Every register, every pipeline stage, every state machine is built from D flip-flops. The edge-triggered behavior creates a clean separation: combinational logic computes during the cycle, flip-flops capture the result at the edge.